Layout generation is an important topic in IC design. For digital circuits a lot of research has been conducted in this area, resulting in a large variety of books and layout generation tools. However, with the ever increasing frequencies, we are facing now significant analog types of artifacts in the IC, introduced during the physical design phase, when schematics are translated to physical ICs via a layout. Moreover, with the trend to systems on chip, analog circuitry and massive amounts of digital circuitry are going to be integrated on the same chip, now called a mixed-signal chip. Compatibility between the high-resolution but low-level analog signals and the relatively large-swing digital signals with their fast transition edges is becoming a severe problem, which makes layout generation a tedious and complex job.