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Rapid Prototyping of Digital Systems: A Tutorial Approach
Rapid Prototyping of Digital Systems: A Tutorial Approach
Date: 12 April 2011, 05:09

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Rapid Prototyping of Digital Systems: A Tutorial Approach
Tutorial I: The 15 Minute Design 2
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
Design Entry using the Graphic Editor
Compiling the Design
Simulation of the Design
Downloading Your Design to the UP 1 or UP 1X Board
6
9
The 10 Minute VHDL Entry Tutorial
10
12
14
17
17
21
22
23
24
24
25
25
30
31
31
31
34
36
38
41
42
43
47
Compiling the VHDL Design
The 10 Minute Verilog Entry Tutorial
Compiling the Verilog Design
Timing Analysis
The Floorplan Editor
Symbols and Hierarchy
Functional Simulation
For additional information
Laboratory Exercises
2 The Altera UP 1 and UP 1X CPLD Boards
2.1
2.2
2.3
2.4
2.5
Programming Jumpers
MAX 7000 Device and UP 1 I/O Features
MAX and FLEX Seven-segment LED Displays
FLEX 10K Device and UP 1 I/O Features
Obtaining a UP 1 or UP 1X Board and Power Supply
3 Programmable Logic Technology
3.1
3.2
3.3
3.4
CPLDs and FPGAs
Altera MAX 7000S Architecture – A Product Term CPLD Device
Altera FLEX 10K Architecture – A Look-Up Table CPLD Device
Xilinx 4000 Architecture – A Look-Up Table FPGA Device

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