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Wireless CMOS Frequency Synthesizer Design
Wireless CMOS Frequency Synthesizer Design
Date: 14 April 2011, 05:39

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The recent boom in the mobile telecommunication market has captured the interest of electronic and communication companies worldwide. In order to cut costs, and to decrease volume and power consumption, research is ongoing which focuses on the integration of a complete RF transceiver on a single die. This book discusses for the first time an important building block in such a single-chip wireless transceiver, that is, the frequency synthesizer. CMOS Wireless Frequency Synthesizer Design starts off with a comprehensive overview of possible synthesizer architectures together with a discussion of the general PLL theory. It goes on to present an easy calculation method of predicting LC-tuned VCO phase noise. Practical designs are presented which illustrate in detail the implementation of monolithic LC-tuned VCOs, using either bonding-wire inductors or hollow planar inductors. It is demonstrated that such designs can achieve the required phase noise specifications using standard CMOS technology. CMOS Wireless Frequency Synthesizer Design also discusses the other PLL building blocks such as the high-speed frequency divider. The phase-switching multi-modulus prescaler architecture, which combines high input frequencies with a programmable division factor, is presented in chapter 6. A concluding chapter combines all the gathered knowledge and presents the first monolithic standard CMOS frequency synthesizer that achieves the DCS-1800 specifications. CMOS Wireless Frequency Synthesizer Design is essential reading for all researchers and practicing engineers working in the design of wireless communication systems requiring highly integrated RF transceivers and frequency synthesizers.
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