Verilog: Frequently Asked Questions: Language, Applications and Extensions | Date: 06 May 2011, 20:09
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This book addresses "front end" questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q&A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and SystemVerilog have also been referred to in this book.
With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of Design, Synthesis or Verification has profound effects on these three stages. This book presents the intricacies of these inter-dependent issues in the context of the Verilog HDL.
Summary: Very good Verilog and hardware design book
Rating: 4
This book tries to do three things: 1) introduce designers to some of the idiosynchrasies and pitfalls of the Verilog language, 2) teach some important basic digital design principles, and 3) go beyond pure functionality and help designers appreciate testability, verification, and emergent system performance issues. It does very well in all, I think. They do not mire themselves down in the detailed syntax or semantics of Verilog except in avoiding the aforementioned pitfalls. On the whole, the design principles are well illustrated. They did reference a web page on metastability and synchronization between clock domains, but by and large, the book is self contained. It seems to me that there is an error in the gated clock discussion in Fig. 2.20. The clock polarity is invered compared with Fig. 2.19 - the latter is correct. Also ~clk needs to be used instead of clk in some of the latch control code in the corresponding Verilog examples. Otherwise, I have found few problems. This book is by far the best of the dozen or so (generally poor) Verilog books I have read.
Summary: Excellent Book for verilog users
Rating: 5
I started writing in verilog HDL in early 1990. When I read this book it gives me lot of of new information that I was not aware of. From students to senior engineers, I strongly suggest to read this book. It provides very good tips to write your code for synthesis and verification. Again, excellent book.
Regards,
VerilogGeek
Summary: Highly recommend!
Rating: 5
I highly recommend this book for students/engineers who have basic knowldges in Verilog and want to know how to improve their design and what they should focus on during their design phase for their project.
This book is well-organized. It starts from basic concept of verilog, followed by the RTL design, and verification. The authors even provides a section called common mistakes to help readers understand the pitfalls they usually make and the side effect of making these mistake.
This book is easy to read. One of the reasons is the authors provide a very good flow for readers to read through the book (from basic to advanced); moreover, the authors also provide explanation for some jargons which beginners are not familiar with. Finally, all of the questions are listed in TOC, which is pretty easy for students/engineers to skip to the topics which interest them.
I believe this book is a must-have in the book shelf. For students, you may ask your library to buy this since it is not cheap. However, it does worth buying if you want to keep it yourself.
PassWord: www.freebookspot.com
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