Verification Techniques for System-Level Design - ISBN:0123706165

Verification Techniques for System-Level Design

Date: 06 May 2011, 18:14

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Book Description
A must-read in formal and semi-formal verification!
Product Description
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs.
First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs.
Formal verification of high-level designs (RTL or higher).
Verification techniques are discussed with associated system-level design methodology.
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Product Details
* Hardcover: 256 pages
* Publisher: Morgan Kaufmann (October 23, 2007)
* Language: English
* ISBN-10: 0123706165
* ISBN-13: 978-0123706164

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