Designing with FPGAs and CPLDs
| Date: 06 May 2011, 00:42
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Note: CD-ROM is not included.
This work helps you choose the right programmable logic devices and development tools; understand the design, verification, and testing issues; and, plan schedules and allocate resources efficiently. You can choose the right programmable logic devices with this guide. "Designing with FPGAs and CPLDs" guides readers through choosing the right programmable logic devices, understanding the design, verification, and testing issues involved with them, and more.
Author presents the proprietary architectures and processes of the assortment of CPLDs and FPGAs on the market to help the reader select the appropriate device.
About the Author
Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASI
Table of Contents
Foreword
Preface
Book Organization
Intended Audience
Content
Support and Feedback
Acknowledgments
Chapter 1 Prehistory: Programmable Logic to ASICs
Objectives
1.1 Programmable Read Only Memories (PROMs)
1.2 Programmable Logic Arrays (PLAs)
1.3 Programmable Array Logic (PALs)
1.4 The Masked Gate Array ASIC
1.5 CPLDs and FPGAs
1.6 Summary
Exercises
Chapter 2 Complex Programmable Logic Devices (CPLDs)
Objectives
2.1 CPLD Architectures
2.2 Function Blocks
2.3 I/O Blocks
2.4 Clock Drivers
2.5 Interconnect
2.6 CPLD Technology and Programmable Elements
2.7 Embedded Devices
2.8 Summary: CPLD Selection Criteria
Exercises
Chapter 3 Field Programmable Gate Arrays (FPGAs)
Objectives
3.1 FPGA Architectures
3.2 Configurable Logic Blocks
3.3 Configurable I/O Blocks
3.4 Embedded Devices
3.5 Programmable Interconnect
3.6 Clock Circuitry
3.7 SRAM vs. Antifuse Programming
3.8 Emulating and Prototyping ASICs
3.9 Summary
Exercises
Chapter 4 Universal Design Methodology for Programmable Devices
Objectives
4.1 What is UDM and UDM-PD?
4.2 Writing a Specification
4.3 Specification Review
4.4 Choosing Device and Tools
4.5 Design
4.6 Verification
4.7 Final Review
4.8 System Integration and Test
4.9 Ship Product!
4.10 Summary
Exercises
Chapter 5 Design Techniques, Rules, and Guidelines
Objectives
5.1 Hardware Description Languages
5.2 Top-Down Design
5.3 Synchronous Design
5.4 Floating Nodes
5.5 Bus Contention
5.6 One-Hot State Encoding
5.7 Design For Test (DFT)
5.8 Testing Redundant Logic
5.9 Initializing State Machines
5.10 Observable Nodes
5.11 Scan Techniques
5.12 Built-In Self-Test (BIST)
5.13 Signature Analysis
5.14 Summary
Exercises
Chapter 6 Verification
Objectives
6.1 What is Verification?
6.2 Simulation
6.3 Static Timing Analysis
6.4 Assertion Languages
6.5 Formal Verification
6.6 Summary
Exercises
Chapter 7 Electronic Design Automation Tools
Objectives
7.1 Simulation Software
7.2 Testbench Generators
7.3 In Situ Tools
7.4 Synthesis Software
7.5 Automatic Test Pattern Generation (ATPG)
7.6 Scan Insertion Software
7.7 Built-In Self-Test (BIST) Generators
7.8 Static Timing Analysis Software
7.9 Formal Verification Software
7.10 Place and Route Software
7.11 Programming Tools
7.12 Summary
Exercises
Chapter 8 Today and the Future
Objectives
8.1 Cores
8.2 Special I/O Drivers
8.3 New Architectures
8.4 ASICs with Embedded FPGA Cells
8.5 Summary
Appendix A Answer Key
Chapter 1, "Prehistory: Programmable Logic to ASICs"
Chapter 2, "Complex Programmable Logic Devices (CPLDs)"
Chapter 3, "Field Programmable Gate Arrays (FPGAs)"
Chapter 4, "Universal Design Methodology for Programmable Devices"
Chapter 5, "Design Techniques, Rules, and Guidelines"
Chapter 6, "Verification"
Chapter 7, "Electronic Design Automation Tools"
Appendix B Verilog Code for Schematics in Chapter 5
Glossary
References
About the Author
Index
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