Embedded SRAMs now dominate CMOS computing chips taking well over half of the total transistor count of high performance ICs. This dominance forces designers to minimize the SRAM layout area imposing a tight transistor density. This transistor circuit density presents two challenges for the test. The first is that virtually all areas of the cells are active and sensitive to particle-related defects. Secondly, parasitic coupling between cells is a major concern. This book addresses both of these problems.